a) Field of the Invention
The present invention relates to packaging of electronic semiconductor devices, especially, a method for manufacturing plastic encapsulated electronic semiconductor devices such as power transistors encapsulated in plastic.
b) Description of the prior art
In general, semiconductor devices require high quality in electric and mechanical characteristics of dielectric strength, durability and thermal radiation, however, it is rather difficult to provide an economical manufacturing process of high quality devices in a practical and available form. In a structural view of electronic devices, packaging of a semiconductor element and a support pad therefor is now very important since the electric and mechanical features in fact depend on the packaged structure of the devices.
Plastic encapsulated semiconductor devices are known some of which include a plastic bottom wall to cover a bottom surface of a support pad on which an electronic element or printed circuit substrate is deposited. For example, a typical semiconductor device of this type is disclosed in U.S. Pat. No. 4,451,973 which sets forth easy encapsulation of semiconductor devices in plastic. In this patent, a power transistor is made by pouring a plastic encapsulating material into a molding cavity wherein a lead frame is placed, and then cutting strips at the small section area connected to bands. Whereas the patent discloses a simple and practical way for manufacture, cut portions of the strips are exposed out of the plastic encapsulating material and therefore apparently results in reduction of dielectric strength, since they may electrically contact or come in close proximity to other objects for short circuit.
In order to avoid such defect, a proposal was made to substantially thoroughly encapsulate the semiconductor chip and support pad except external leads extending out of the plastic encapsulating material, as exhibited by Japanese Patent Disclosure No. 60-130129 published July 11, 1985. It discloses a method of forming a plastic encapsulation by gripping an end of the support pad by means of pins movable in a metallic mold. In this molding technique, there is a clear difficulty in detecting an exact timing for starting travel of pins during the molding operation as mentioned hereinafter in detail. In other words, the molding technique does neither teach any method for fully filling up spaces formed by movement of the pins with plastic encapsulating material, nor any practical way for exactly determining a timing to start travel of the pins. Therefore, in some cases, undesirable holes are formed in the plastic encapsulating material due to delayed movement of the pins during molding operation. Adversely, hasty movement of the pins may cause the support pad to tilt to a slight angle because of injection pressure of the plastic encapsulating material loaded on the support pad, thereby resulting in uneven thickness of a plastic layer formed beneath the bottom surface of the support pad. The plastic layer having the different thicknesses deteriolates quality of the devices due to reduced thermal radiation and cracks in the layer or exposure of the support pad out of the layer.
Meanwhile, many attempt have been made for development of plastic encapsulated semiconductor devices by the inventor of the present invention. As known from Japanese Patent Disclosure No. 61-2348 published Jan. 8, 1986, one of his inventions indicates a mold device which includes a cavity and two gates oppositely provided in both sides of the cavity. In this mold structure, however, the provision of two sets of feed runners and gates complicates the construction and maintenance of the mold.